好例３

1998.9.4

以下の英文は私のところに送られてきたDMのE-Mail版（商品名などは変えてあります）です。ライティングの心得のある方が書かれたのでしょう。次の点で非常に良くできています。

• 概要が先頭に書かれている

• 明確な目的を持ってパラグラフ構成されている

• パラグラフの先頭に要約文が書かれている

• キーワードが主語になっている

RACE operates directly on IC layout data bases (GDSII), and has been used to successfully convert chips, macro blocks, and standard cell libraries between different process technologies. Some of RACE user's include Intel Corp., OKI Semiconductor, T.S.M.C., Xilinx, Cirrus Logic, and SGS-Thomson. Applications for RACE include:

1. Conversion: RACE can convert a data base (GDSII) from one process to another. RACE supports non-linear scaling; this means that you can apply different scaling rules for different types of layout structures. Examples include scaling n or p doped transistors by different factors, or scaling transistors and power metal differently.

　

2. Optimization: RACE can automatically adjust layout to improve yield and increase performance. One example is inserting extract contacts, another is widening power busses. RACE can be used to fix timing problems, by having it resize a specific transistor(s) to correct W, L values. Imagine the power of fixing problems like this in layouts and not having to re-place and route the chip.

　

3. Compaction: RACE can compact your mask data to minimum design rule size. Or RACE can be used to compact your layout if only one or two process rules change. With RACE, each design can be compacted to its smallest size to boost your manufacturing yield.

RACE can convert any layout style, e.g. custom, standard cells, macro blocks, or synthesized layouts. RACE operates directly on the layout by moving edge by edge, just like a human designer would do it. RACE can insert automatically or maintain 45 degree transistors and wires, and allows a free choice of grid on each layer. Circuit functionality and netlist are not changed.

RACE is a very sophisticated and flexible tool for moving designs between sub-micron processes. It makes IC design reuse really practical. Proven designs may be combined together, and then automatically converted to a new sub-micron process, while being compacted and optimized.

At DAC '96 two new versions of RACE were introduced. RACE STAR supports hierarchical conversion of standard cell designs. RACE MEGA allows conversion of circuits of any size, without limitation, and without requiring very large machine memory. RACE STAR and RACE MEGA may be combined for use to provide hierarchy and unlimited circuit size.